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Intel’s Haswell brings transactional memory tech

Intel's Haswell brings transactional memory tech

Intel’s Haswell architecture is going to bring a supercomputing technology to the desktop: transactional memory.

Intel has released further details of its next-next generation processor architecture, Haswell, and its transaction memory functionality.

Due to take over from the yet-to-be-released Ivy Bridge, Haswell will be constructed on the same process size but with a new microarchitecture. The company has previously detailed some of the improvements that will bring, including the Haswell New Instructions, but this week’s announcement is something a bit special.

Dubbed Transaction Synchronisation Extensions, or TSX, the technology provides extensions to the processor’s instruction set that allows programmers to specify particular regions of code as suitable for transactional synchronisation.

As Intel’s James Reinders puts it in his blog post on the matter: ‘With transactional synchronisation, the hardware can determine dynamically whether threads need to serialise through lock-protected critical sections, and perform serialisation only when required. This lets the processor expose and exploit concurrency that would otherwise be hidden due to dynamically unnecessary synchronisation.

Code engineered to take advantage of TSX could prove pretty nippy. Reinders explains that if the programmer has done his or her job correctly and the transactional execution completes successfully, all memory operations performed in that code segment will appear to have occurred instantaneously from the perspective of other processors in the system.

The technology works in a similar way to a transactional database: operations can be performed in isolation, making it possible for a multicore processor to run code more efficiently. Like a database, it’s also possible to roll back a transaction if necessary, while TSX promises to do away with the requirement to lock resources during computation in order to prevent modification by other process threads.

Put simply: with TSX, Intel promises, coders will be able to push their workloads onto multiple processing cores without worrying about complex and performance-sapping fine-grain locking techniques.

Transactional memory isn’t new. IBM’s BlueGene/Q supercomputer uses a very similar method, while other HPC platforms have their own implementations. TSX will mark the first time that transactional memory technology has been available at a consumer level, however, and it holds the potential to be a significant disruptive influence in the multithreading arena.

Sadly, as with any new instruction set, it could be a while before consumers start to see the benefit. With Haswell due to launch in 2013, expect a teething period of a year or two for developers to figure out the best ways to implement TSX in their own applications.

Article source: http://feedproxy.google.com/~r/bit-tech/news/~3/sJykmSV2wk0/1

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